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FEATURES 18 MSPS Correlated Double Sampler (CDS) 6 dB to 40 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Preblanking Function 10-Bit 18 MSPS A/D Converter 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power CMOS 48-Lead LQFP Package APPLICATIONS PC Cameras Digital Still Cameras
Complete 10-Bit 18 MSPS CCD Signal Processor AD9804
FUNCTIONAL BLOCK DIAGRAM
PBLK AVDD AVSS CLPOB DRVDD CLP 6dB TO 40dB CDS VGA 10-BIT ADC 10 DOUT DRVSS
CCDIN
CLP BANDGAP REFERENCE CLPDM 10 INTERNAL BIAS
VR T VRB
VGA GAIN REGISTER
CML
DVDD
AD9804
DIGITAL INTERFACE
INTERNAL TIMING
DVSS
PRODUCT DESCRIPTION
The AD9804 is a complete analog signal processor for CCD applications. It features an 18 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9804's signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled VGA, black level clamp, and a 10-bit A/D converter. The internal VGA gain register is programmed through a 3-wire serial digital interface.
SL SCK
SDATA SHP SHD DATACLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
ANALOG SPECIFICATIONS (T
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION MAXIMUM CLOCK RATE
AD9804-SPECIFICATIONS
MIN
to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 18 MHz, unless otherwise noted.)
Min -20 -65 2.8 3.0 85 18 500 1.0 100 1024 4 38 6 40 32 10 10 2.0 2.0 1.0 8 42 Typ Max +85 +150 3.6 Unit C C V mW MHz mV V p-p mV Steps dB dB LSB Bits Bits Guaranteed V V V
CORRELATED DOUBLE SAMPLER (CDS) Allowable CCD Reset Transient1 Max Input Range before Saturation1 Max CCD Black Pixel Amplitude1 VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Range (VGA Gain Curve Shown in Figure 5) Min Gain (Code 95) Max Gain (Code 1023) BLACK LEVEL CLAMP Clamp Level (At ADC Output) A/D CONVERTER Resolution No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (VRT) Reference Bottom Voltage (VRB)
NOTES 1 Input signal characteristics defined as follows:
500mV TYP RESET TRANSIENT 100mV MAX OPTICAL BLACK PIXEL
1V MAX INPUT SIGNAL RANGE
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current
Specifications subject to change without notice.
(DRVDD = 2.7 V, CL = 20 pF.)
Symbol VIH VIL IIH IIL CIN VOH VOL IOH IOL Min 2.1 0.6 10 10 10 2.1 0.6 50 50 Typ Max Unit V V A A pF V V A A
-2-
REV. 0
AD9804 TIMING SPECIFICATIONS (C = 20 pF, f
L CLK
= 18 MHz, timing shown in Figures 1 and 2.)
Symbol tCONV tADC tSHP tSHD tCDM tCOB tS1 tS2 tID tINH tOD tH Min Typ 55.6 27.7 14 14 10 10 27 27 3.0 Max Unit ns ns ns ns Pixels Pixels ns ns ns ns 16 ns ns Cycles MHz ns ns ns ns ns
Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK Hi/Low Pulsewidth SHP Pulsewidth SHD Pulsewidth CLPDM Pulsewidth CLPOB Pulsewidth1 SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock Delay Inhibited Clock Period DATA OUTPUTS Output Delay Output Hold Time Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read
20 10 10 4 2 20 20 10
6.0
14.5 7.6 9
fSCLK tLS tLH tDS tDH tDV
10 10 10 10 10 10
NOTES 1 Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Specifications subject to change without notice
ABSOLUTE MAXIMUM RATINGS With Respect To AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS
ORDERING GUIDE
Model
Min Max -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 +3.9 +3.9 +3.9 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 300 Unit V V V V V V V V V C C
Temperature Range -20C to +85C
Package Description Thin Plastic Quad Flatpack (LQFP)
Package Option ST-48
Parameter AVDD DVDD DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL BYP1-4, CCDIN Junction Temperature Lead Temperature (10 sec)
AD9804JST
THERMAL CHARACTERISTICS
Thermal Resistance 48-Lead LQFP Package JA = 92C/W
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9804 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
-3-
AD9804
PIN CONFIGURATION
SDATA SL NC DVSS DVDD DVSS RSTB DVSS
48 47 46 45 44 43 42 41 40 39 38 37
NC 1 NC 2 (LSB) D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 D8 11 (MSB) D9 12 NC = NO CONNECT
VRT CML
SCK
VRB
PIN 1 IDENTIFIER
36 35 34
NC
AVSS NC 33 AVDD
AD9804
TOP VIEW (Not to Scale)
32 31 30 29 28
BYP4 NC CCDIN BYP2
BYP1 AVDD 26 AVSS
27 25 13 14 15 16 17 18 19 20 21 22 23 24
AVSS
DVDD NC
DRVSS DVSS DATACLK
PBLK CLPOB
SHP
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 2, 18, 24, 31 34, 36, 45 3-12 13 14 15, 41, 42, 44 16 17, 40 19 20 21 22 23 25, 26, 35 27, 33 28 29 30 32 37 38 39 43 46 47 48
Mnemonic NC D0-D9 DRVDD DRVSS DVSS DATACLK DVDD PBLK CLPOB SHP SHD CLPDM AVSS AVDD BYP1 BYP2 CCDIN BYP4 CML VRT VRB RSTB SL SDATA SCK
Type NC DO P P P DI P DI DI DI DI DI P P AO AO AI AO AO AO AO DI DI DI DI
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
DRVDD
Description Internally Not Connected Digital Data Outputs Digital Output Driver Supply Digital Output Driver Ground Digital Ground Digital Data Output Latch Clock Digital Supply Preblanking Clock Input Black Level Clamp Clock Input CDS Sampling Clock for CCD's Reference Level CDS Sampling Clock for CCD's Data Level Input Clamp Clock Input Analog Ground Analog Supply Internal Bias Level Decoupling Internal Bias Level Decoupling Analog Input for CCD Signal Internal Bias Level Decoupling Internal Bias Level Decoupling A/D Converter Top Reference Voltage Decoupling A/D Converter Bottom Reference Voltage Decoupling Chip Reset Control. Active Low Serial Digital Interface Load Pulse. Serial Digital Interface Data Serial Digital Interface Clock
-4-
SHD CLPDM NC
REV. 0
AD9804
TIMING DIAGRAMS
CCD SIGNAL
N
N+1
N+2
N+9
N+10
tID
SHP
tID
tS1
SHD
tS2
tCP
tINH
DATACLK
tOD
OUTPUT DATA N-10 N-9
tH
N-8 N-1 N
NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 1. Pixel Rate Timing
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
HORIZONTAL BLANKING
DUMMY PIXELS
EFFECTIVE PIXELS
CCD SIGNAL
CLPOB
CLPDM
PBLK
OUTPUT DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
NOTES: 1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB. 2. PBLK SIGNAL IS OPTIONAL. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
Figure 2. Typical Line Clamp Timing
REV. 0
-5-
AD9804
PROGRAMMING THE SERIAL INTERFACE Table I. VGA Gain Register Contents (Default Value x096) MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 Gain (dB)
0
0
0
1
0
1 1
1 1
1 1
1 1
1 1
1 * * * 1 1
1
1
1
1
1 1
1 1
1 1
0 1
6.0 * * * 39.965 40.0
RNW SDATA 0
ADDRESS BITS 1 0 0 0
DATA BITS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS
SCK
tDH
tLS
SL NOTES: 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. RNW = READ, NOT WRITE. SET LOW FOR WRITE OPERATION. 3. INTERNAL VGA GAIN REGISTER UPDATE OCCURS AT SL RISING EDGE.
tLH
Figure 3. Serial Write Operation
RNW SDATA 1
ADDRESS BITS 1 0 0 0
DATA BITS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
tDS
SCK
tDH
tDV
tLS
SL
tLH
NOTES: 1. RNW = READ, NOT WRITE. SET HIGH FOR READ OPERATION. 2. THE RNW BIT AND THE FOUR ADDRESS BITS MUST BE WRITTEN TO THE AD9804. SDATA IS LATCHED ON SCK RISING EDGES. 3. SERIAL DATA FROM VGA GAIN REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK FALLING EDGES.
Figure 4. Serial Readback Operation
-6-
REV. 0
AD9804
VARIABLE GAIN AMPLIFIER (VGA) OPERATION DETAILS
The VGA stage provides a gain range of 6 dB to 40 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems (such as ADI's AD9803), the equivalent gain range is 0 dB to 34 dB. The VGA gain curve is divided into two separate regions. When the VGA Gain Register code is between 0 and 511, the curve follows a (1 + x)/(1 - x) shape, which is similar to a "linear-indB" characteristic. From code 512 to code 1023, the curve follows a "linear-in-dB" shape. The exact VGA gain can be calculated for any Gain Register value by using the following two equations: Code Range Gain Equation (dB) 0-511 Gain = 20 log10 ([658 + code]/[658 - code]) + 3.6 512-1023 Gain = (0.0354)(code) + 3.6 As shown in the Analog Specifications, only the VGA gain range from 2 dB to 36 dB has been specified. This corresponds to a VGA gain code range of 95 to 1023.
40
capacitor. The AD9804 performs the dc restoration, CDS, gain adjustment, black level correction, and analog-to-digital conversion. The AD9804's digital output data is then processed by the image processing ASIC. The internal registers of the AD9804 used to control gain, offset level, and other functions are programmed by the ASIC or microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE.
Generating the Reset (RSTB) Signal
After power-on, the AD9804 must be reset using Pin 43 (RSTB). The reset pulse must be an active low signal, which goes low for at least 100 ns after the power supplies have settled. After the RSTB signal returns high, the AD9804 is internally reset to the default VGA gain register value. If a system reset pulse is not available, a simple RC network may be used, as shown in Figure 7. The time constant of this network should be comparable to the power-on time of the AD9804's power supplies. For example, if the power supplies have a power-on time of 10 ms, the RC network should have a time constant of 10 ms, giving R = 10 k and C = 1.0 F. Serial writes to the AD9804 internal registers must not be performed until 20 s after the reset pulse has occurred. This allows enough time for internal calibration routines to be completed. SDATA and SCK may be active before the reset sequence, but SL should be held logic HIGH until 20 s or more after the reset. Alternatively, placing series resistors close to the digital output pins may help reduce noise.
Grounding and Decoupling Recommendations
34
VGA GAIN - dB
28
22
16
10
4
0
127
255 383 511 639 767 VGA GAIN REGISTER CODE
895
1023
Figure 5. VGA Gain Curve
APPLICATIONS INFORMATION
The AD9804 is a complete Analog Front-End (AFE) product for PC camera, digital still camera, and camcorder applications. As shown in Figure 6, the CCD image (pixel) data is buffered and sent to the AD9804 analog input through a series input
As shown in Figure 7, a single ground plane is recommended for the AD9804. This ground plane should be as continuous as possible, particularly around Pins 25 through 39. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. A single clean power supply is recommended for the AD9804, but a separate digital driver supply may be used for DRVDD (Pin 13). DRVDD should always be decoupled to DRVSS (Pin 14), which should be connected to the analog ground plane. Advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing digital power dissipation, and reducing potential noise coupling. If the digital outputs (Pins 3-12) must drive a load larger than 20 pF, buffering is recommended to reduce digital code transition noise.
CCD VOUT 0.1 F
AD9804
ADCOUT CCDIN VGA GAIN
DIGITAL OUTPUTS SERIAL INTERFACE DIGITAL IMAGE PROCESSING ASIC
BUFFER V-DRIVE CCD TIMING
CDS/CLAMP TIMING TIMING GENERATOR
Figure 6. System Block Diagram
REV. 0
-7-
AD9804
3V ANALOG SUPPLY 10k 1.0 F 0.1 F 1.0 F 1.0 F SERIAL INTERFACE 3 0.1 F
48 47 46 45 44 43 42 41 40 39 38 37
NC
1 PIN 1 IDENTIFIER
NC 2 (LSB) D0 D1
3 4
36 35 34
NC AVSS NC 0.1 F 0.1 F 3V ANALOG SUPPLY 0.1 F CCD SIGNAL 0.1 F 0.1 F 0.1 F 3V ANALOG SUPPLY
D2 5 D3 6 D4 D5 D6 9 D7
8
AVDD 33 BYP4
32
AD9804
TOP VIEW (Not to Scale)
31 30
7
NC CCDIN
BYP2 29 BYP1
28
10
D8 11 (MSB) D9
12 13 14 15 16 17 18 19 20 21 22 23 24
AVDD AVSS 26 AVSS
27 25
DRVDD
DATACLK
CLPDM NC
NC PBLK CLPOB SHP SHD
DRVSS DVSS
DVDD
DATA OUTPUTS
10
NC = NO CONNECT 6 CLOCK INPUTS
3V DRIVER SUPPLY
0.1 F
0.1 F 3V ANALOG SUPPLY
Figure 7. AD9804 Circuit Configuration
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead, LQFP (ST-48)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
0.354 (9.00) BSC SQ
48 1 37 36
TOP VIEW
(PINS DOWN)
0.276 (7.00) BSC SQ
25
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0 MIN
12 13 24
0.019 (0.5) BSC 7 0
0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35)
0.006 (0.15) SEATING 0.002 (0.05) PLANE
-8-
REV. 0
C01633-0-10/00 (rev. 0)
SDATA SL
DVDD VRB
NC DVSS RSTB DVSS DVSS
VRT CML
SCK

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